Energy Performance of Floating-Point Matrix Multiplication on FPGAs

Floating-point matrix multiplication is a basic kernel in scientific computing. It has been shown that implementations of this kernel on FPGAs can achieve high sustained performance [1]. However, to the best of our knowledge, existing work on FPGA-based floating-point matrix multiplication considers the optimization of latency or area only. In this paper, we analyze the impact of various parameters on the energy dissipation of two floating-point matrix multiplication algorithms developed by us. Due to space limitation, the algorithms are not presented here. Details of the algorithms (Algorithm 1 and Algorithm 2) can be found in [1]. We identify several parameters that affect the energy dissipation of the algorithms. These include the number of pipeline stages within the floating-point units, the block size for block matrix multiplication, and the number of PEs configured on the device. These parameters give rise to a large implementation space for the algorithms. This implementation space is explored using domain-specific modeling developed by us, a high-level approach to quickly evaluate the energy performance of various designs [2]. For small problem sizes, zero padding is required if deeply pipelined floating-point units are employed. Therefore, even though these implementations achieve higher clock speeds, they dissipate more energy than the implementations with moderately pipelined floating-point units. For large problem size, the effect of zero padding is negligible. In this case, using floating-point units that has the highest “throughput per unit area” achieves the best energy dissipation performance. When the matrix size is large, block matrix multiplication needs to be employed. With small block sizes, deeply pipelined implementations dissipate much more energy than moderately pipelined implementations because of zero padding. The impact of zero padding dwindles as the block size increases. Therefore, the block size depends on both the problem size and the floating-point units employed. We implemented our algorithms using Xilinx ISE 5.2i [3], with Xilinx Virtex-II Pro XC2VP125 as our target device. Low level power simulation using XPower [3] was performed to verify the energy results of the high-level modeling. In our experiments, series of matrices were fed into the architecture consecutively so that zero padding is not needed. Our experiments show that the energy dissipation estimated by the highlevel modeling is within 12% of the actual values obtained by the low level simulation. Theoretically, Algorithm 2 uses